1. Field of the Invention
The present invention relates to techniques for forming barrier layers to prevent resist poisoning in dual damascene structures in semiconductor devices.
2. Description of the Related Art
As features become smaller in semiconductor devices, it becomes more desirable to reduce interconnection delays through the selection of materials used in the interconnects and associated dielectric layers. The propagation delays through the interconnects are proportional to the resistance of the interconnects and the capacitance offered by the dielectric. In order to minimize the delays low resistance conductors such as copper are typically used in the interconnects. Significant recent efforts have been directed to the selection of appropriate low-k dielectric materials to reduce the capacitance and thereby reduce the interconnect propagation delays.
One drawback to the use of copper in the interconnects and metallization conductor is its tendency to poison adjacent dielectric layers. Copper diffuses easily into dielectric layers and barrier layers and diminishes the electrical insulation qualities of the dielectric. Incorporating nitrogen into a dielectric barrier layer is commonly employed method to reduce this electrical leakage. Particularly when silicon carbide is used as a barrier layer, doping the barrier layer with nitrogen is known to significantly diminish the amount of electrical leakage into the barrier.
Low-k dielectric material layers exhibit lower dielectric constants than silicon oxides. These improvements are generally related to the increased porosity of the low-k materials. In part due to the increased porosity, the low-k materials are particularly prone to diffusion of nitrogen from adjacent barrier films. During the formation of trenches and vias, photoresist masks are used to control the locations of etches. Frequently, nitrogen from the barrier layers diffuses into the photoresist and poisons the mask. This poisoning prevents full development of the mask. As a result, residual portions of the photoresist fail to dissolve and remain in the trench or via. During subsequent etching of the trench in a via-first dual damascene approach to interlayer interconnects, the photoresist residue will prevent the formation of a trench having the desired shape or result in other defects. Often, the residue combines with the etch chemicals to mushroom. Thus, the residue resulting from the photoresist poisoning produces a defective trench.
Accordingly, it is desirable to prevent the nitrogen from combining with photoresist materials so that trenches and vias may be formed in techniques such as dual damascene schemes without defects caused by the poisoned photoresist residue.
To achieve the foregoing, the present invention provides a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is subsequently formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of the photoresist layer. One application of the present invention is the process of forming dual damascene interconnect structures. Nitrogen poisoning present in conventional methods results in the formation of defects in the trench formation from residual photoresist mask material.
In one aspect, the invention provides a process for preventing resist poisoning in a semiconductor device. A first barrier layer containing silicon carbide and nitrogen is deposited on a surface located to control electrical leakage from a conductor. A nitrogen-free second barrier layer is deposited on top of the first barrier layer. A low-k dielectric layer is formed over the second barrier layer. A photoresist layer is formed and etched to form a photoresist mask covering at least a portion of the low-k dielectric layer.
In another aspect, the invention provides a process of forming a dual damascene structure in a semiconductor device using a nitrogen-free second barrier layer. The process involves first forming a via into the first low-k dielectric layer. A photresist mask is formed and the second low-k dielectric layer is etched to form a trench.
In another aspect, the invention provides a dual damascene process of forming an interconnect using a nitrogen doped first barrier layer and a nitrogen-free second barrier layer. Both barrier layers are formed using the same tool.
These and other features and advantages of the present invention are described below with reference to the drawings.